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?1 CXP85632/85640 e95510-ps cmos 8-bit single chip microcomputer description the CXP85632/85640 is a cmos 8-bit micro- computer which consists of a/d converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, i 2 c bus interface, pwm output, remote control receiver, hsync counter and watchdog timer as well as basic configuration like 8-bit cpu, rom, ram and i/o port. also this ic provides power-on reset function and sleep function which enables to lower power consumption. features a wide instruction set (213 instructions) to cover various types of data. ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 333ns at 12mhz operation incorporated rom 32k bytes (CXP85632) 40k bytes (cxp85640) incorporated ram 1888 bytes (excluding the closed caption decoder and on-screen display vram) peripheral functions ?a/d converter 8 bits, 6 channels, successive approximation method (conversion time of 26.7s/12mhz) ?serial interface 8-bit clock, sync type, 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer ?closed caption decoder incorporated decode slicer, conforming to fcc, 8 13 dots, 192 character types, 15 character colors, 4 lines of 34 characters, italic, underline, vertical scroll, 15 frame background colors/half blanking ?on-screen display (osd) function 12 16 dots, 128 character types, 15 character colors, 4 lines of 24 characters, 8 frame background colors/half blanking, edging per line (half dot), vertical scroll jitter elimination circuit ?i 2 c bus interface ?pwm output 8 bits, 4 channels ?remote control receiver circuit incorporated 6-stage fifo 8-bit pulse measurement counter ?hsync counter 2 channels ?watchdog timer interruption 15 factors, 15 vectors, multi-interruption possible standby mode sleep package 64-pin plastic sdip/qfp piggyback/evaluation chip cxp85690 64-pin ceramic psdip (accommodates custom font) purchase of sony's i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conform to the i 2 c standard specifications as defined by philips. sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin sdip (piastic) 64 pin qfp (piastic) structure silicon gate cmos ic
?2 CXP85632/85640 vin xlc exlc r g b i ys ym hsync vsync si so sck ec to rmc hsc0 hsc1 an0 to an5 cvss cv dd cap rex data slicer cc decoder on screen display serial interface unit 8bit timer/counter 0 remocon hsync counter 0 hsync counter 1 a/d converter 6ch fifo 3 2 int2 int1 int0 scl1 scl0 sda1 sda0 i 2 c bus interface unit 8bit pwm 4ch watchdog timer prescaler/ time base timer spc700 cpu core rom 32k/40k bytes clock generator/ system control ram 1888 bytes vss v dd mp rst xtal extal pwm0 to pwm3 pa0 to pa7 8 pb0 to pb7 8 pc0 to pc7 8 pd0 to pd7 8 pe0 to pe2 3 pf0 to pf7 8 interrupt controller port a port b port c port d port e port f 8bit timer 1 2 block diagram
?3 CXP85632/85640 pin assignment (top view) 64-pin sdip 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 pc3 pc2 pc1 pc0 ec/pd7 rmc/pd6 hs1/pd5 hs0/pd4 si/pd3 so/pd2 sck/pd1 int2/pd0 hsync/pa7 vsync/pa6 rst vss xtal extal pa5/an5 pa4/an4 pa3/an3 pa2/an2 pa1/an1 pa0/an0 cvss cap rex vin cv dd int1/pb7 pb6 pb5 pc4 pc5 pc6 pc7 pf0/pwm0 pf1/pwm1 pf2/pwm2 pf3/pwm3 pf4/scl0 pf5/scl1 pf6/sda0 pf7/sda1 pe0/to pe1 pe2/int0 mp vss v dd nc exlc xlc ym ys i b g r pb0 pb1 pb2 pb3 pb4 note) 1. nc (pin 46) must be connected to v dd . 2. vss (pins 16 and 48) must be connected to gnd. 3. mp (pin 49) must be connected to gnd. 4. cap (pin 26) must be connected to cv ss via a capacitor. 5. rex (pin 27) must be connected to cv dd via a resistor of 33k .
?4 CXP85632/85640 pin assignment (top view) 64-pin qfp hs1/pd5 hs0/pd4 si/pd3 s0/pd2 sck/pd1 int2/pd0 hsync/pa7 vsync/pa6 rst vss xtal extal pa5/an5 pa4/an4 pa3/an3 pa2/an2 pa1/an1 pa0/an0 cvss 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 pf3/pwm3 pf4/scl0 pf5/scl1 pf6/sda0 pf7/sda1 pe0/to pe1 pe2/int0 mp vss v dd nc exlc xlc ym ys i b g 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 pd6/rmc pd7/ec pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pf0/pwm0 pf1/pwm1 pf2/pwm2 52 53 54 55 56 57 58 59 60 63 64 61 62 cap rex vin cv dd int1/pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 r 20 21 22 23 24 25 26 27 28 29 30 31 32 note) 1. nc (pin 40) must be connected to v dd . 2. vss (pins 10 and 42) must be connected to gnd. 3. mp (pin 43) must be connected to gnd. 4. cap (pin 20 ) must be connected to cv ss via a capacitor. 5. rex (pin 21) must be connected to cv dd via a resistor of 33k .
?5 CXP85632/85640 pin functions pin name pa0/an0 to pa5/an5 pa6/vsync pa7/hsync pb0 to pb6 pb7/int1 pc0 to pc7 pd0/int2 pd1/sck pd2/so pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec pe0/to pe1 pe2/int0 pf0/pwm0 to pf3/pwm3 pf4/scl0 pf5/scl1 pf6/sda0 pf7/sda1 r, g, b, i, ys, ym i/o/analog input i/o/input i/o/input i/o i/o/input i/o i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input i/o/output i/o i/o/input output/output output/i/o output/i/o output i/o functions analog inputs to a/d converter. (6 pins) osd display vertical sync signal input. osd display horizontal sync signal input. input for external interruption request. active at the falling edge. input for external interruption request. active at the falling edge. serial clock i/o. serial data output. serial data input. hsync counter (ch0) input. hsync counter (ch1) input. remote control receiver circuit input. external event input for timer/counter. rectangular wave output for timer/counter. input for external interruption request. active at the falling edge. 8-bit pwm outputs. (4 pins) transfer clock i/o for i 2 c bus interface. (2 pins) transfer data i/o for i 2 c bus interface. (2 pins) (port a) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port b) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma sync current. (8 pins) (port e) 3-bit i/o port. i/o can be set in a unit of single bits. (3 pins) (port f) 8-bit output port with large current (12ma) n-ch open drain output. lower 4 bits are 12v drive and upper 4 bits are 5v drive. osd display 6-bit outputs. (6 pins)
?6 CXP85632/85640 pin name exlc xlc vin cap rex cv dd cv ss extal xtal rst mp nc v dd vss input output input input output i/o input osd display clock oscillation i/o. oscillator frequency is determined by external l and c. input of external composite video signal. input a 2vp-p signal via a capacitor. capacitor connection for the data slicer. connect a capacitor between cap and cv ss . resistor connection for the data slicer. connect a 33k resistor between rex and cv dd . positive power supply for data slicer. gnd for data slicer. system clock oscillator crystal connection. when using an external clock, input to extal pin and leave xtal pin open. low level active system reset. this pin acts as i/o pin and outputs low level through incorporated power-on reset function when the power turned on. (mask option) test mode input. must be connected to gnd. not connected. under normal conditions, connect to v dd . positive power supply. gnd. connect two v ss pins to gnd. i/o functions
?7 CXP85632/85640 i/o circuit format for pins data bus port a data port a direction rd (port a) a ip vsync, hsync input polarity schmitt input "0" when reset port a data port a direction data bus rd (port a) port a function selection ??when reset aa aa ip a/d converter input multiplexer ??when reset input protection circuit port b, c data port b, c direction data bus rd (port b, c) int1 aa aa ip ??when reset schmitt input port a port a port b port c 2 pins 6 pins 16 pins hi-z hi-z hi-z pin when reset circuit format pa0/an0 to pa5/an5 pb0 to pb6 pb7/int1 pc0 to pc7 pa6/vsync pa7/hsync
?8 CXP85632/85640 port d data port d direction data bus rd (port d) int2, si, hs0, hs1, rmc, ec * large current 12ma aa aa ip schmitt input ??when reset * port d data port d direction data bus rd (port d) sck only * large current 12ma sck, so serial output enable schmitt input a ip ??when reset * port e function selection to port e direction port e data data bus int0 schmitt input only for pe2 rd (port e) ??when reset ??when reset for pe0, 1 ??when reset for pe0, 1 ??when reset for pe2 aa ip port d port d port e 6 pins 2 pins 3 pins hi-z hi-z pe0, pe1: high pe2: hi-z pin when reset circuit format pd1/sck pd2/so pe0/to pe1 pe2/int0 pd0/int2 pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec
?9 CXP85632/85640 scl, sda aa aa aaaaa port f data * large current 12ma i 2 c output enable a a ip schmitt input scl, sda (i 2 c circuit) to internal i 2 c pins (to scl1 for scl0) bus sw ??when reset * port f selection port f data pwm0 to pwm3 large current 12ma * 12v drive voltage ??when reset ??when reset * port f port f 4 pins 4 pins 6 pins 2 pins pin when reset circuit format pf4/scl0 pf5/scl1 pf6/sda0 pf7/sda1 hi-z hi-z hi-z oscillation halted r g b i ys ym pf0/pwm0 to pf3/pwm3 exlc xlc aa aa r, g, b, i, ys, ym output becomes active by data writing to output polarity register. aaaa aaaa output polarity ??when reset oscillator control aa aa exlc aa aa a a ip osd display clock aa aa ip xlc
?10 CXP85632/85640 2 pins 1 pin pin when reset circuit format rst oscillation low level extal xtal aa aa aa aa ip aa aa extal xtal diagram indicates equivalent circuit during oscillation. feedback resistor is disconnected during stop. (this device does not enter in the stop mode.) a a schmitt input pull-up resistor from power-on reset circuit (mask option) mask option op
?11 CXP85632/85640 * 1 v in and v out should not exceed v dd + 0.3v. * 2 the large current output port is port d (pd) and port f (pf). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium voltage tolerance output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd v in v out v outp i oh s i oh i ol i olc s i ol topr tstg p d ?.3 to +7.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +15.0 ? ?0 15 20 100 ?0 to +75 ?5 to +150 1000 600 v v v v ma ma ma ma ma ? ? mw mw pf0 to pf3 pins total of all output pins excludes large current output port (value per pin) large current output port (value per pin * 2 ) total of all output pins sdip qfp item symbol ratings unit remarks absolute maximum ratings (vss = 0v reference) 5.5 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v ? item symbol min. max. unit remarks 4.5 3.5 2.5 4.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v dd * 1 this device does not enter in the stop mode. * 2 pa, pb, pc, pe0, pe1, scl0, scl1, sda0, sda1 pins. * 3 int2, sck, so, si, hs0, hs1, rmc, ec, int1, hsync, vsync, rst pins. * 4 specifies only during external clock input. * 5 cv dd and v dd should be set to the same voltage. recommended operating conditions (vss = 0v reference) supply voltage data slicer supply voltage high level input voltage low level input voltage operating temperature cv dd v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/2 or 1/4 frequency dividing mode guaranteed operation range for 1/16 frequency dividing or sleep mode guaranteed data hold range for stop mode * 1 * 5 * 2 * 3 extal pin * 4 * 2 * 3 extal pin * 4
?12 CXP85632/85640 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 4.5v, i ol = 12.0ma high level output voltage low level output voltage input current i/o leakage current open drain output leak current (n-ch tr off case) i 2 c bus switch connection impedance (output tr off case) supply current input capacitance 4.0 3.5 18 0.9 5.0 10 3 10.0 20 ? ma pf 50 10 120 30 ma ma ? ? w 0.4 0.6 1.5 0.4 0.6 40 ?0 ?00 ?0 v v v v v ? ? ? ? 0.5 ?.5 ?.5 v v pa to pd, pe, r, g, b, i, ys, ym pa to pd, pe, r, g, b, i, ys, ym, pf0 to pf3, rst * 1 pd, pf pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst * 2 pa to pe, hsync, vsync, r, g, b, i, ys, ym, rst * 2 pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd * 3 cv dd stop mode * 4 v dd = 5.5v, termination of 12mhz oscillation v dd = 5.5v sleep mode v dd = 5.5v, 12mhz crystal oscillation (c 1 = c 2 = 15pf) pa to pe, scl, sda, exlc, extal, vin, rst 1mhz clock 0v for all pins excluding measured pins item symbol pin condition min. typ. max. unit v oh v ol i iz i loh r bs i dd i ddsl i ddst i cvdd c in i ihe i ihl i ilr dc characteristics (ta = ?0 to +75?, vss = 0v reference) * 1 rst pin is specified only when the power-on reset circuit is selected with mask option. * 2 in rst pin, the input current is specified when the pull-up resistor is selected; the leakage current when no resistor is selected. * 3 when all pins are open. specifies only when the osd oscillation stops. * 4 this device does not enter in the stop mode. 1/2 frequency dividing mode v dd = 5.5v 12mhz crystal oscillation (c 1 = c 2 = 15pf)
?13 CXP85632/85640 ac characteristics (1) clock timing * 1 t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits. (cpu clock selection) t sys (ns) = 2000/fc (upper 2 bits = ?0?, 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") system clock frequency system clock input pulse width system clock rise and fall times event counter input clock pulse widtth event counter input clock rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec ec mhz ns ns ns ms item system pin condition min. max. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig 1, fig 2 external clock drive fig. 3 fig. 3 37.5 t sys * 1 + 50 typ. 12.0 200 20 (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc fig. 2. clock applied condition aaaa a aa a aaaa aaaa a aa a aaaa crystal oscillator ceramic oscillator extal xtal external clock extal xtal open c 1 c 2 fig. 3. event count clock timing ec t eh t el t ef t er 0.2v dd 0.8v dd
?14 CXP85632/85640 (2) serial transfer (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level widths si input set-up time (for sck - ) si input hold time (for sck - ) sck ? so delay time system pin condition min. max. unit note) the load condition for the sck output mode, so output delay time is 50pf + 1ttl. fig. 4. serial transfer timing 0.2v dd 0.8v dd t kl t kh so t kcy t sik t ksi 0.2v dd 0.8v dd t kso 0.2v dd 0.8v dd output data input data si sck
?15 CXP85632/85640 resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt * 1 v ft * 2 t conv t samp v ian an0 to an5 ta = 25? v dd = 5.0v vss = 0v ?0 4910 160/f adc * 3 12/f adc * 3 0 10 4970 8 ? 70 5030 v dd bits lsb mv mv ? ? v item symbol pin condition min. typ. max. unit (3) a/d converter characteristics (ta = ?0 to +75c, v dd = 4.5 to 5.5v, vss = 0v reference) linearity error v zt v ft analog input ff h fe h 01 h 00 h digital conversion value fig. 5. definitions for a/d converter terms * 1 v zt : digital conversion values change between 00 h ?? 01 h . * 2 v ft : digital conversion values change between 0e h ?? 0f h . * 3 f adc indicates the below values due to the bit 6 (cks) of a/d control registor (adc: 00f9 h ) and the bit 7 (pck1) and bit 6 (pck0) of clock control registor (clc: 00fe h ) 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 f adc = f c cks pck1, 0 0 ( f /2 selection) 1 ( f selection) f adc = f c /2 f adc = f c /8
?16 CXP85632/85640 external interrupt high and low level widths reset input low level width int0 int1 int2 rst 1 32/fc ? ? item symbol pin condition min. max. unit t ih t il t rsl power supply rise time power supply cutt-off time t r t off v dd power-on reset repeated power-on reset 0.05 1 50 ms ms item symbol pin condition min. max. unit (4) interrupt, reset input (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) (5) power-on reset * 1 (ta = ?0 to +75?, vss = 0v reference) 0.2v dd 0.8v dd t ih t il int0 int1 int2 (falling edge) * 1 specified only when power-on reset function is selected. 0.2v 0.2v 4.5v v dd t r t off take care when turning on power. fig. 6. interrupt input timing t rsl 0.2v dd rst fig. 7. rst input timing fig. 8. power-on reset
?17 CXP85632/85640 (6) i2c bus timing (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width set-up time for repeated transfers data hold time data set-up time sda, scl rise time sda, scl fall time set-up time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 * 1 250 4.7 100 1 300 khz ? ? ? ? ? ? ns ? ns ? symbol pin condition min. max. unit * 1 for data hold time, the scl rise time is not taken into account so that 300ns must be exceeded. fig. 9. i 2 c bus transfer data timing p st t su; sto t su; sta t hd; sta t su; dat t high t hd; dat t f t r t low t hd; sta s p t buf sda scl fig. 10. i 2 c device recommended circuit i 2 c device i 2 c device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) a pull-up resistor must be connected to sda0 (or sda1), and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 w or less) can be used to reduce spike noise caused by crt flashover.
?18 CXP85632/85640 (7) osd (on screen display) timing (ta = ?0 to +75c, v dd = 4.5 to 5.5v, vss = 0v reference) item osd clock frequency hsync pulse width hsync after-write rise and fall times vsync before-write rise and fall times f osc t hwd t hcg t vcg exlc xlc hsync hsync vsync fig. 12 fig. 11 fig. 11 fig. 11 4 1.2 16.5 200 1.0 mhz ? ns ? symbol pin condiiton unit min. max. fig. 11. osd timing 0.8v dd 0.2v dd t hcg t hwd hsync for opol register (01fd h ) bit 7 at ? 0.8v dd 0.2v dd t vcg vsync for opol register (01fd h ) bit 6 at ? fig. 12. lc oscillator circuit connection l c 2 c 1 exlc xlc r * 1 * 1 the xlc series resistor can reduce the occurrence of undersired radiation.
?19 CXP85632/85640 (8) data slicer external circuit (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item vin pin coupling capacitor cap pin capacitor rex pin pull-up resistor composite video signal input c vin ccap rrex video in vin cap rex vin 0.47 4700 33 2.0 ? pf k w vp-p symbol pin min. unit typ. max. fig. 13. data slicer external recommeded circuit b or more of temperature characteristics is recommended. b or more of temperature characteristics is recommended. remarks cv dd rex v in cap cvss ccap c 1 r 2 video in c vin r 1 rrex 5.0v [recommended constant] r 1 = 100 w (error: 5%; allowable power dissipation: 1/8 w or more) r 2 = 1m w (error: 5%; allowable power dissipation: 1/8 w or more) c 1 = 820pf (ceramic), b or more of temperature characteristics is recommended.
?20 CXP85632/85640 supplement fig. 14. spc700 series recommended oscillation circuit c 2 c 1 aaaa a aa a aaaa extal xtal rd aaaa a aa a aaaa extal xtal rd (i) manufacturer kinseki ltd. model fc (mhz) 5 5 0 * 1 c 1 (pf) c 2 (pf) rd ( w ) circuit example (i) 15 15 0 * 1 (i) * 1 the xtal series resistor can reduce the effect of electrostatic discharge noise. item inclusion reset pin pull-up resistor power-on reset circuit non-existent non-existent existent existent mask option table river eletec co., ltd. 12.0 12.0 hc-49/u03 hc-19/u (-s)
?21 CXP85632/85640 fig. 15. characteristics curves i dd ? supply current [ma] i dd vs. v dd (fc = 12mhz, ta = 25?, typical) v dd ? supply voltage [v] 234 56 0.1 100 i dd vs. fc frequency dividing mode 1 16 sleep mode frequency dividing mode 1 4 frequency dividing mode 1 2 10 1 sleep mode frequency dividing mode 1 16 frequency dividing mode 1 4 frequency dividing mode 1 2 i dd ? supply current [ma] 50 45 40 35 30 25 20 15 10 5 0 fc ? system clock [mhz] 16 12 8 4 parameter curve for osd oscillation l vs. c (theoretically calculated value) 10mhz 12mhz 14mhz 100 10 0 l ? inductance [h] 50 100 c 1 , c 2 ? capacitance [pf] f osc = c = c 1 // c 2 (v dd = 5v, ta = 25?, typical) 16mhz 1 2 p lc
?22 CXP85632/85640 package outline unit: mm package structure molding compound lead treatment lead material package weight sony code eiaj code jedec code sdip-64p-01 42 alloy solder plating epoxy / phenol resin 64pin sdip (plastic) 750mil sdip064-p-0750-a 57.6 ?0.1 + 0.4 64 33 132 1.778 19.05 17.1 ?0.1 + 0.3 0?to 15 0.25 ?0.05 + 0.1 0.5 min 4.75 ?0.1 + 0.4 3 min 0.5 0.1 0.9 0.15 8.6g sony code eiaj code jedec code 23.9??.4 20.0?.1 1.0 0.4 ?0.1 + 0.15 14.00.1 1 19 20 32 33 51 52 64 0.15 ?0.05 + 0.1 2.75 ?0.15 16.3 0.1 ?0.05 + 0.2 0.8 0.2 m 0.12 0.15 +?.4 17.9??.4 +0.4 + 0.35 64pin qfp(plastic) qfp?4p?01 * qfp064??420 package material lead treatment lead material package weight epoxy resin solder/palladium copper /42 alloy package structure plating 1.5g

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